diff --git a/src/Accessing_VRAM_and_OAM.md b/src/Accessing_VRAM_and_OAM.md index 7f54d609..0ae05536 100644 --- a/src/Accessing_VRAM_and_OAM.md +++ b/src/Accessing_VRAM_and_OAM.md @@ -46,7 +46,7 @@ start of Mode 0 is to disable all the individual STAT interrupts except Mode 0 (STAT bit 3), enable STAT interrupts (IE bit 1), disable IME (by executing `di`), and use the `halt` instruction. This allows use of the entire Mode 0 on one line and Mode 2 on the following line, -which sum to 165 to 288 dots. For comparison, at single speed (4 dots +which sum to 165 to 288 dots. For comparison, at normal speed (4 dots per machine cycle), a copy from stack that takes 9 cycles per 2 bytes can push 8 bytes (half a tile) in 144 dots, which fits within the worst case timing for mode 0+2. diff --git a/src/CGB_Registers.md b/src/CGB_Registers.md index e0000678..a38441c0 100644 --- a/src/CGB_Registers.md +++ b/src/CGB_Registers.md @@ -115,7 +115,7 @@ manually terminating a HBlank Transfer. In both Normal Speed and Double Speed Mode it takes about 8 μs to transfer a block of $10 bytes. -That is, 8 M-cycles in Normal Speed Mode [\[1\]](imgs/hdma_single_speed.png), +That is, 8 M-cycles in Normal Speed Mode [\[1\]](imgs/hdma_normal_speed.png), and 16 "fast" M-cycles in Double Speed Mode [\[2\]](imgs/hdma_double_speed.png). Older MBC controllers (like MBC1-3) and slower ROMs are not guaranteed to support General Purpose or HBlank DMA, that's because there are always 2 bytes @@ -150,7 +150,7 @@ loaded VRAM bank in bit 0, and all other bits will be set to 1. "KEY1" 7:"Current speed" 0:"Switch armed" }} -- **Current speed** (*Read-only*): `0` = Single-speed mode, `1` = Double-speed mode +- **Current speed** (*Read-only*): `0` = Normal-speed mode, `1` = Double-speed mode - **Switch armed** (*Read/Write*): `0` = No, `1` = Armed This register is used to prepare the Game Boy to switch between CGB @@ -171,7 +171,7 @@ ENDIF The CGB is operating in Normal Speed Mode when it is first turned on. Note that using the Double Speed Mode increases the power consumption; therefore, it -would be recommended to use Single Speed whenever possible. +would be recommended to use Normal Speed whenever possible. In Double Speed Mode the following will operate twice as fast as normal: diff --git a/src/MBC3.md b/src/MBC3.md index 8269f925..a3a85077 100644 --- a/src/MBC3.md +++ b/src/MBC3.md @@ -91,4 +91,4 @@ Year-10000-Proof, provided that the cartridge gets used at least every ### Delays When accessing the RTC Registers, it is recommended to wait 4 µs -(4 M-cycles in Single Speed Mode) between any separate accesses. +(4 M-cycles in Normal Speed Mode) between any separate accesses. diff --git a/src/Rendering.md b/src/Rendering.md index d7eb171b..4f2baa6b 100644 --- a/src/Rendering.md +++ b/src/Rendering.md @@ -9,7 +9,7 @@ The main implication of this rendering process is the existence of **raster effe The most famous raster effect is modifying the [scrolling registers](<#LCD Position and Scrolling>) between scanlines to create a ["wavy" effect](https://gbdev.io/guides/deadcscroll#effects). A "**dot**" = one 222 Hz (≅ 4.194 MHz) time unit. -Dots remain the same regardless of whether the CPU is in [Double Speed mode](<#FF4D — KEY1/SPD (CGB Mode only): Prepare speed switch>), so there are 4 dots per Single Speed M-cycle, and 2 per Double Speed M-cycle. +Dots remain the same regardless of whether the CPU is in [Double Speed mode](<#FF4D — KEY1/SPD (CGB Mode only): Prepare speed switch>), so there are 4 dots per Normal Speed M-cycle, and 2 per Double Speed M-cycle. :::tip NOTE diff --git a/src/STAT.md b/src/STAT.md index 21b783b3..4b5313f7 100644 --- a/src/STAT.md +++ b/src/STAT.md @@ -2,7 +2,7 @@ :::tip TERMINOLOGY -A *dot* is the shortest period over which the PPU can output one pixel: is it equivalent to 1 T-cycle on DMG or on CGB Single Speed mode or 2 T-cycles on CGB Double Speed mode. On each dot during mode 3, either the PPU outputs a pixel or the fetcher is stalling the [FIFOs](<#Pixel FIFO>). +A *dot* is the shortest period over which the PPU can output one pixel: is it equivalent to 1 T-cycle on DMG or on CGB Normal Speed mode or 2 T-cycles on CGB Double Speed mode. On each dot during mode 3, either the PPU outputs a pixel or the fetcher is stalling the [FIFOs](<#Pixel FIFO>). ::: diff --git a/src/Serial_Data_Transfer_(Link_Cable).md b/src/Serial_Data_Transfer_(Link_Cable).md index 70a9f381..a8f4de02 100644 --- a/src/Serial_Data_Transfer_(Link_Cable).md +++ b/src/Serial_Data_Transfer_(Link_Cable).md @@ -36,7 +36,7 @@ incoming bit is shifted in from the other side: }} - **Transfer enable** (*Read/Write*): If `1`, a transfer is either requested or in progress. -- **Clock speed** \[*CGB Mode only*\] (*Read/Write*): If set to `1`, enable high speed serial clock (~256 kHz in single-speed mode) +- **Clock speed** \[*CGB Mode only*\] (*Read/Write*): If set to `1`, enable high speed serial clock (~256 kHz in normal-speed mode) - **Clock select** (*Read/Write*): `0` = External clock ("slave"), `1` = Internal clock ("master"). The master Game Boy will load up a data byte in SB and then set diff --git a/src/Timer_and_Divider_Registers.md b/src/Timer_and_Divider_Registers.md index e6bb1c0f..fe06debf 100644 --- a/src/Timer_and_Divider_Registers.md +++ b/src/Timer_and_Divider_Registers.md @@ -52,7 +52,7 @@ due to a timer overflow, the old value is transferred to TIMA.
- + diff --git a/src/imgs/hdma_single_speed.png b/src/imgs/hdma_normal_speed.png similarity index 100% rename from src/imgs/hdma_single_speed.png rename to src/imgs/hdma_normal_speed.png
Clock selectIncrement everyFrequency (Hz)
DMG, SGB2, CGB in single-speed modeSGB1CGB in double-speed mode
DMG, SGB2, CGB in normal-speed modeSGB1CGB in double-speed mode
00256 M-cycles 4096 ~4194 8192
014 M-cycles 262144~268400524288