@@ -254,6 +254,105 @@ final class Wasmi64BinOp: WasmOperation {
254254 }
255255}
256256
257+ public enum WasmAtomicRMWType : UInt8 , CaseIterable {
258+ case i32Add = 0x1e
259+ case i64Add = 0x1f
260+ case i32Add8U = 0x20
261+ case i32Add16U = 0x21
262+ case i64Add8U = 0x22
263+ case i64Add16U = 0x23
264+ case i64Add32U = 0x24
265+
266+ case i32Sub = 0x25
267+ case i64Sub = 0x26
268+ case i32Sub8U = 0x27
269+ case i32Sub16U = 0x28
270+ case i64Sub8U = 0x29
271+ case i64Sub16U = 0x2a
272+ case i64Sub32U = 0x2b
273+
274+ case i32And = 0x2c
275+ case i64And = 0x2d
276+ case i32And8U = 0x2e
277+ case i32And16U = 0x2f
278+ case i64And8U = 0x30
279+ case i64And16U = 0x31
280+ case i64And32U = 0x32
281+
282+ case i32Or = 0x33
283+ case i64Or = 0x34
284+ case i32Or8U = 0x35
285+ case i32Or16U = 0x36
286+ case i64Or8U = 0x37
287+ case i64Or16U = 0x38
288+ case i64Or32U = 0x39
289+
290+ case i32Xor = 0x3a
291+ case i64Xor = 0x3b
292+ case i32Xor8U = 0x3c
293+ case i32Xor16U = 0x3d
294+ case i64Xor8U = 0x3e
295+ case i64Xor16U = 0x3f
296+ case i64Xor32U = 0x40
297+
298+ case i32Xchg = 0x41
299+ case i64Xchg = 0x42
300+ case i32Xchg8U = 0x43
301+ case i32Xchg16U = 0x44
302+ case i64Xchg8U = 0x45
303+ case i64Xchg16U = 0x46
304+ case i64Xchg32U = 0x47
305+
306+ var type : ILType {
307+ switch self {
308+ case . i32Add, . i32Add8U, . i32Add16U,
309+ . i32Sub, . i32Sub8U, . i32Sub16U,
310+ . i32And, . i32And8U, . i32And16U,
311+ . i32Or, . i32Or8U, . i32Or16U,
312+ . i32Xor, . i32Xor8U, . i32Xor16U,
313+ . i32Xchg, . i32Xchg8U, . i32Xchg16U:
314+ return . wasmi32
315+ case . i64Add, . i64Add8U, . i64Add16U, . i64Add32U,
316+ . i64Sub, . i64Sub8U, . i64Sub16U, . i64Sub32U,
317+ . i64And, . i64And8U, . i64And16U, . i64And32U,
318+ . i64Or, . i64Or8U, . i64Or16U, . i64Or32U,
319+ . i64Xor, . i64Xor8U, . i64Xor16U, . i64Xor32U,
320+ . i64Xchg, . i64Xchg8U, . i64Xchg16U, . i64Xchg32U:
321+ return . wasmi64
322+ }
323+ }
324+
325+ func naturalAlignment( ) -> Int64 {
326+ switch self {
327+ case . i32Add8U, . i64Add8U,
328+ . i32Sub8U, . i64Sub8U,
329+ . i32And8U, . i64And8U,
330+ . i32Or8U, . i64Or8U,
331+ . i32Xor8U, . i64Xor8U,
332+ . i32Xchg8U, . i64Xchg8U:
333+ return 1
334+ case . i32Add16U, . i64Add16U,
335+ . i32Sub16U, . i64Sub16U,
336+ . i32And16U, . i64And16U,
337+ . i32Or16U, . i64Or16U,
338+ . i32Xor16U, . i64Xor16U,
339+ . i32Xchg16U, . i64Xchg16U:
340+ return 2
341+ case . i32Add, . i64Add32U,
342+ . i32Sub, . i64Sub32U,
343+ . i32And, . i64And32U,
344+ . i32Or, . i64Or32U,
345+ . i32Xor, . i64Xor32U,
346+ . i32Xchg, . i64Xchg32U:
347+ return 4
348+ case . i64Add, . i64Sub,
349+ . i64And, . i64Or,
350+ . i64Xor, . i64Xchg:
351+ return 8
352+ }
353+ }
354+ }
355+
257356final class Wasmi32UnOp : WasmOperation {
258357 override var opcode : Opcode { . wasmi32UnOp( self ) }
259358 let unOpKind : WasmIntegerUnaryOpKind
@@ -2144,3 +2243,16 @@ final class WasmAtomicStore: WasmOperation {
21442243 super. init ( numInputs: 3 , numOutputs: 0 , attributes: [ . isMutable] , requiredContext: [ . wasmFunction] )
21452244 }
21462245}
2246+
2247+ final class WasmAtomicRMW : WasmOperation {
2248+ override var opcode : Opcode { . wasmAtomicRMW( self ) }
2249+
2250+ let op : WasmAtomicRMWType
2251+ let offset : Int64
2252+
2253+ init ( op: WasmAtomicRMWType , offset: Int64 ) {
2254+ self . op = op
2255+ self . offset = offset
2256+ super. init ( numInputs: 3 , numOutputs: 1 , attributes: [ . isMutable] , requiredContext: [ . wasmFunction] )
2257+ }
2258+ }
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