Control and Status Registers support -RISC-V

[Maleehaakbar]

Description

I work on custom Andes chip and emulate interrupts using CLIC in Renode in non-vectored CLIC mode.
However , Renode have incomplete support of MTVT ,MNXTI and other control and status registers for RISCV.
Will renode plan to provide support for hardware vectoring mode of CLIC and related CSRs in near future?

If not, kindly give some guidelines on how I provide support for these registers.

[p-woj]

Hi, could you provide some details about which CSRs you mean? We believe all of the standard ones from the proposed specification should be implemented - do you mean some nonstandard registers like MTVT2?

It would also be very helpful if you could share some software that fails due to the incompletely supported registers.

[Maleehaakbar]

The partial support of mtvt is present in tlib submodule but it is not present outside the tlib submodule.
For example:
#define CSR_MTVT 0x307 /* unratified as of 2024-06; smclic extension */

So, at the backend mtvt CSR support is present, however in C# at the front end, there is no support and because of this, the code fails in interrupt code of zephyr and CPU aborts.
(Machine timer is working fine but CPU aborts due to interrupt service routine not properly execute).

[Maleehaakbar]

Partial support of mtvt is present in tlib submodule. Now, I fully provide the support for mtvt CSR for RiscV32 .My code is working fine now. I can open the PR to contribute to renode public repository having support of mtvt CSR that help to run code in CLIC hardware-vectored mode.
Following shows the support of MTVT in my renode `console .

RegisterValue MTVT
available for 'get' and 'set'

[PiotrZierhoffer]

Hi @Maleehaakbar

Absolutely, please do open a PR towards https://github.com/antmicro/tlib/ and https://github.com/renode/renode-infrastructure

[Maleehaakbar]

Hi, I open the PR on both repositories.
renode/renode-infrastructure#119
antmicro/tlib#17