ppc: TimeBase SPRs aren't emulated properly #2256
Description
Hello! Currently the TBU, TBL and DEC SPRs will always return 0, who can cause some issues, this is especially bad since there isn't a way to write to SPRs in the PPC Target, so if the user needs them, .
I was able to re enable Qemu's support for them in this commit and it seemed to work (though my testing wasn't very torough), however, I'm not sure what the best way of exposing this in unicorn would be as I'm assuming just hardcoding the TB Freq and initialising it only for the 6XX/7XX CPUs isn't the prefered way to re enable this. Because of that, I am also opening this issue to know how enabling support for this would be desired.
Here's the code I used to test TimeBase stuff, it's just a modified ver of test_ppc32_spr_time, should be useful in verifying the issues
static void test_ppc32_spr_time(void)
{
uint32_t r3_val;
uc_engine *uc;
char code_dec[] = "\x7c\x76\x02\xa6"; // mfspr r3, DEC
uc_common_setup(&uc, UC_ARCH_PPC, UC_MODE_32 | UC_MODE_BIG_ENDIAN, code_dec,
sizeof(code_dec) - 1);
OK(uc_emu_start(uc, code_start, code_start + sizeof(code_dec) - 1, 0, 0));
uc_reg_read(uc, UC_PPC_REG_3, &r3_val);
printf("DEC: 0x%08x\n", BEINT32(r3_val));
OK(uc_close(uc));
char code_tbur[] = "\x7c\x6d\x42\xa6"; // mfspr r3, TBUr
uc_common_setup(&uc, UC_ARCH_PPC, UC_MODE_32 | UC_MODE_BIG_ENDIAN, code_tbur,
sizeof(code_tbur) - 1);
OK(uc_emu_start(uc, code_start, code_start + sizeof(code_tbur) - 1, 0, 0));
uc_reg_read(uc, UC_PPC_REG_3, &r3_val);
printf("TBUr: 0x%08x\n", BEINT32(r3_val));
OK(uc_close(uc));
char code_tblr[] = "\x7c\x6c\x42\xa6"; // mfspr r3, TBLr
uc_common_setup(&uc, UC_ARCH_PPC, UC_MODE_32 | UC_MODE_BIG_ENDIAN, code_tblr,
sizeof(code_tblr) - 1);
OK(uc_emu_start(uc, code_start, code_start + sizeof(code_tblr) - 1, 0, 0));
uc_reg_read(uc, UC_PPC_REG_3, &r3_val);
printf("TBLr: 0x%08x\n", BEINT32(r3_val));
OK(uc_close(uc));
}