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Add behavior of the HDMA HBlank mode in halt mode #577

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Merged
avivace merged 2 commits into from
Nov 3, 2024
Merged

Add behavior of the HDMA HBlank mode in halt mode #577

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2c64a98
Add behavior of the HDMA HBlank mode in halt mode
alloncm Nov 1, 2024
6e4e320
Add test rom for HDMA HBlank halt behaviour
alloncm Nov 3, 2024
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5 changes: 4 additions & 1 deletion src/CGB_Registers.md
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Expand Up @@ -79,7 +79,10 @@ the program execution continues during the "spaces" between each data
block. Note that the program should not change the Destination VRAM bank
(FF4F), or the Source ROM/RAM bank (in case data is transferred from
bankable memory) until the transfer has completed! (The transfer should
be paused as described below while the banks are switched)
be paused as described below while the banks are switched).

Upon halting the CPU (using the [halt instruction](<#Using the HALT Instruction>)),
the transfer will also be halted and will be resumed only when the CPU resumes execution ([test rom](https://github.com/alloncm/MagenTests?tab=readme-ov-file#vram-dma-hblank-mode) exhibiting this behaviour).

Reading from Register FF55 returns the remaining length (divided by $10,
minus 1), a value of $FF indicates that the transfer has completed. It
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