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1. pipelined-RISCV-core pipelined-RISCV-core Public

   A 32-bit pipelined RISC-V CPU (RV32I subset) with forwarding and load-use hazard handling, implemented and verified in Verilog.

   Verilog

2. 32-bit-RISCV-Single-Cycle-Core 32-bit-RISCV-Single-Cycle-Core Public

   A Verilog implementation of a 32-bit Single-Cycle RISC-V Processor.

   Verilog

3. Booth-Wallace Booth-Wallace Public

   ASIC Design Flow of Signed 8x8 Booth-Wallace Multiplier (Radix-4)

   Verilog 1

4. Signed-Booth-Multiplier Signed-Booth-Multiplier Public

   Hardware implementation of a Signed 8x8-bit Multiplier using Radix-4 Booth Encoding in Verilog

   Verilog

5. ASYNC-FIFO ASYNC-FIFO Public

   A Verilog implementation of Asynchronous FIFO in Xilinx Vivado

   Verilog

6. Neetcode-250 Neetcode-250 Public

   Neetcode-250 C++ Answers

   C++