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implement mtvt CSR to support CLIC vectored mode #119

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implement mtvt CSR to support CLIC vectored mode #119

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3 changes: 2 additions & 1 deletion src/Emulator/Cores/RiscV/RegisterDescription.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -393,7 +393,8 @@ public static void AddCSRFeature(ref List<GDBFeatureDescriptor> features, uint r
csrGroup.Registers.Add(new GDBRegisterDescriptor((uint)RiscV32Registers.MEDELEG, registerWidth, "medeleg", intType, "csr"));
csrGroup.Registers.Add(new GDBRegisterDescriptor((uint)RiscV32Registers.MIDELEG, registerWidth, "mideleg", intType, "csr"));
}


csrGroup.Registers.Add(new GDBRegisterDescriptor((uint)RiscV32Registers.MTVT, registerWidth, "mtvt","", "csr"));
csrGroup.Registers.Add(new GDBRegisterDescriptor((uint)RiscV32Registers.MSTATUS, registerWidth, "mstatus", "", "csr"));
csrGroup.Registers.Add(new GDBRegisterDescriptor((uint)RiscV32Registers.MISA, registerWidth, "misa", "", "csr"));
csrGroup.Registers.Add(new GDBRegisterDescriptor((uint)RiscV32Registers.MIE, registerWidth, "mie", "mie_type", "csr"));
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14 changes: 14 additions & 0 deletions src/Emulator/Cores/RiscV/RiscV32Registers.cs
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Expand Up @@ -278,6 +278,18 @@ public RegisterValue SPTBR
}
}
[Register]
public RegisterValue MTVT
{
get
{
return GetRegisterValue32((int)RiscV32Registers.MTVT);
}
set
{
SetRegisterValue32((int)RiscV32Registers.MTVT, value);
}
}
[Register]
public RegisterValue MSTATUS
{
get
Expand Down Expand Up @@ -773,6 +785,7 @@ protected override void InitializeRegisters()
{ RiscV32Registers.STVAL, new CPURegister(388, 32, isGeneral: false, isReadonly: false, aliases: new [] { "STVAL" }) },
{ RiscV32Registers.SIP, new CPURegister(389, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SIP" }) },
{ RiscV32Registers.SATP, new CPURegister(449, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SATP", "SPTBR" }) },
{ RiscV32Registers.MTVT, new CPURegister(775, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MTVT" }) },
{ RiscV32Registers.MSTATUS, new CPURegister(833, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MSTATUS" }) },
{ RiscV32Registers.MISA, new CPURegister(834, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MISA" }) },
{ RiscV32Registers.MEDELEG, new CPURegister(835, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MEDELEG" }) },
Expand Down Expand Up @@ -811,6 +824,7 @@ public enum RiscV32Registers
SIP = 389,
SATP = 449,
SPTBR = 449,
MTVT= 775,
MSTATUS = 833,
MISA = 834,
MEDELEG = 835,
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